regarding the change of names mentioned in the document, such as mitsubishi electric and mitsubishi xx, to renesas technology corp. the semiconductor operations of hitachi and mitsubishi electric were transferred to renesas technology corporation on april 1st 2003. these operations include microcomputer, logic, analog and discrete devices, and memory chips other than drams (flash memory, srams etc.) accordingly, although mitsubishi electric, mitsubishi electric corporation, mitsubishi semiconductors, and other mitsubishi brand names are mentioned in the document, these names have in fact all been changed to renesas technology corp. thank you for your understanding. except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. note : mitsubishi electric will continue the business operations of high frequency & optical devices and power devices. renesas technology corp. customer support dept. april 1, 2003 to all our customers
m5m5 y416cwg -55hi, -70hi 2002.04.05 ver. 5.1 4194304 -bit (262144-word by 16-bi t) c mos s tat ic ram mi t subishi lsis * typical parameter indicates the value for the center of distribution at 2.3v, and not 100% tested. 1 description the m5m5 y416c is a f amil y o f low v oltage 4-mbit static rams organized as 262144-words b y 16-bit, f abricated b y mitsubishi's high-per f ormance 0.18m cmos technolog y. the m5m5 y416c is suitable f or memor y applications where a simple inter f acing , batter y operating and batter y backup are the important design objecti v es. m5m5 y416cwg is packaged in a csp (chip scale package), with the outline o f 7.0mm x 8.5mm, ball matrix o f 6 x 8 (48ball) and ball pitch o f 0.75mm. it gi v es the best solution f or a compaction o f mounting area as well as f lexibilit y o f wiring pattern o f printed circuit boards. features - single 1.65~2.3v power supply - small stand-b y current: 0.1a (2.3v, t y p.) - no clocks, no re f resh - data retention suppl y v oltage =1.3v - all inputs and outputs are ttl compatible. - eas y memor y expansion b y s1#, s2, bc1# and bc2# - common data i/o - three-state outputs: or-tie capability - oe pre v ents data contention in the i/o bus - process technolog y: 0.18m cmos - package: 48ball 7.0mm x 8.5mm csp pin configuration a0 ~ a17 dq1 ~ dq16 s1# w# oe bc1# address input data input / output chip select input 1 write control input output enable input lower b y te (dq1 ~ 8) pin function vcc gnd power supply ground supply bc2# upper b y te (dq9 ~ 16) s2 chip select input 2 (top view) outline: 48fja nc: no connection * d on't connect e3 ball to v oltage le v el more than 0v 1 2 3 4 5 6 a b c d e f g dq3 a7 dq1 s2 vcc gnd dq6 a2 s1# dq2 dq4 dq5 dq7 a1 a4 a6 a5 a17 a16 a15 a0 a3 ncor gnd* a14 oe# bc2# dq15 dq13 dq12 dq10 bc1# dq16 dq14 gnd vcc dq1 1 dq8 w# a13 a12 n . c. dq9 n . c. a11 a10 a9 a8 h those are summarized in the part name table below. 30 ma (10mhz) 3ma (1mhz) version, operating temperature part name power supply access time max. stand-b y c urrent ( a) ratings (max.) acti ve current (2.3v, max) icc1 70c 85c25c i-version -40 ~ +85c m5m5 y416cwg -70hi 1.65 ~ 2.3v 70 ns * t y pical 40c 25c 40c 15 821 0.20.1 n c m5m5 y416cwg -55hi 1.65 ~ 2.3v 55 ns
m5m5 y416cwg -55hi, -70hi 2002.04.05 ver. 5.1 4194304 -bit (262144-word by 16-bi t) c mos s tat ic ram mi t subishi lsis 2 function the m5m5 y416cwg is organized as 262144-words by 16-bit. these de v ices operate on a single +1.65~2.3v power suppl y, and are directl y ttl compatible to both input and output. its f ull y static circuit needs no clocks and no re f resh, and makes it use f ul. the operation mode are determined b y a combination o f the de v ice control inputs bc1# , bc2# , s1# , s2 , w# and oe#. each mode is summarized in the f unction table. a write operation is executed whene v er the low le v el w# o v erlaps with the low le v el bc1# and/or bc2# and the low le v el s1# and the high le v el s2. the address(a0~a17) must be set up be f ore the write c ycle and must be stable during the entire c yc le. a read operation is executed b y s etting w at a high le v el and oe# at a low le v el while bc1# and/or bc2# and s1# and s2 are in an acti v e state(s1=l,s2=h). when setting bc1# at the high le v el and other pins are in an acti v e stage , upper-b yt e are in a selectable mode in which both reading and writing are enabled, and lower-b yt e are in a non-selectable mode. and when setting bc2# at a high le v el and other pins are in an acti v e stage, lower-b yt e are in a selectable mode and upper-b y te are in a non-selectable mode. when setting bc1# and bc2# at a high le v el or s1# at a high le v el or s2 at a low le v el, the chips are in a non- selectable mode in which both reading and writing are disabled. in this mode, the output stage is in a high- impedance state, allowing or-tie with other chips and memor y expansion b y bc1#, bc2# and s1#, s2. the power suppl y current is reduced as low as 0.1a(25 c , vcc=1.65v, t y pical), and the memor y data can be held at +1.3v power suppl y, enabling batter y back-up operation during power f ailure or power-down operation in the non- selected mode. block diagram function table mode s2 w# h x x high-z bc1#bc2# oe# dq1~8 x x non selection dq9~16 icc high-z standby high-z high-z h x ll h din high-z acti ve h h l h read high-z dout acti ve l h h l acti ve h h l acti ve h l high-z high-z acti ve h l h h high-z h l dout h l l read dout acti ve h l din ll x write din acti ve h high-z h h high-z high-z non selection x h h x x standby write h h l l write din acti ve x h l h read high-z acti ve l dout h high-z s1# h l l l l l l l x l l l x x high-z x x non selection high-z standby l l x x high-z x x non selection high-z standby h memor y array 262144 words x 16 bits clock g enerator a 0 a 1 a 16 a 17 s2 bc2# w# oe# dq 8 dq 1 dq 16 dq 9 - vcc gnd s1# bc1# note1: "h" and "l" in this table mean v ih and v il, respecti v ely . note2: " x" in this table should be "h" or "l".
m5m5 y416cwg -55hi, -70hi 2002.04.05 ver. 5.1 4194304 -bit (262144-word by 16-bi t) c mos s tat ic ram mi t subishi lsis 3 absolute maximum ratin gs pf 10 v i =gnd, v i =25mvrms, f =1mhz v o = gnd,v o =25mvrms, f =1mhz c i c o symbol parameter limits conditions units a ma ma v icc 1 icc 2 icc 4 v ih v il i o icc 3 v oh i oh = -0.1ma v ol i ol =0.1ma i i v i =0 ~ vcc bc1# and bc2#=v ih or s1#=v ih or s2=v il or oe#=v ih , v i/o =0 ~ vcc vcc+0.2 0.4 0.7xvcc -0.2 * 1.3 0.5 0.2 1 3018 1 3 max t yp min dc electrical characteristics f = 10mhz f = 1mhz - - - - - suppl y v oltage input v oltage output v oltage power dissipation operating temperature storage temperature v mw conditions ta=25c 700 - 65 ~ +150 ratings v cc v i v o p d t a t stg -0.3 * ~ +2.7 -0.3 * ~ vcc + 0.3 (max. 2.7v) 0 ~ vcc s ymbol parameter units - 40 ~ +85 i- v ersion with respect to gnd f = 10mhz f = 1mhz 1.5 3018 3 1.5 - with respect to gnd with respect to gnd ( vcc=1.65~ 2.3v, unless otherwise noted) high-le v el input v oltage low-le v el input v oltage high-le vel output volta ge low-le v el output v oltage input leakage current output leakage current acti v e suppl y c urrent ( ac,mos le v el ) ( ac,ttl le v el ) acti v e suppl y c urrent stand b y s uppl y current ( ac,mos le v el ) ( ac,ttl le v el ) stand b y s uppl y current other inputs= 0 ~ vcc note 3: direction for current flowing into ic is indicated as positive (no mark) note 4: typical parameter indicates the value for the center of distribution at 2.3v, and not 100% tested. capacitance (vcc=1.65 ~ 2.3v, unless otherwise noted) s ymbol parameter conditions limits max t yp min units input capacitance output capacitance * -0.7v in case o f ac (pulse width 30ns) bc1# and bc2# 0.2v, s1# 0.2v, s2 vcc-0.2v other inputs 0.2v or vcc-0.2v output - open (duty 100%) < = < = > = bc1# and bc2#=v il , s1#=v il ,s2=v ih < = other pins =v ih or v il output - open (duty 100%) bc1# and bc2#=v ih or s1#=v ih or s2=v il * -0.7v in case o f ac (pulse width 30ns) < = < = 10 c c a 0.1 - ~ +85c ~ +25c - 1 ~ +40c - 0.2 2 - 15 (1) s1# vcc - 0.2v, > = other inputs = 0 ~ vcc s2 0.2v, (2) other inputs = 0 ~ vcc bc1# and bc2# vcc - 0.2v s1# 0.2v, s2 vcc - 0.2v < = > = (3) > = other inputs = 0 ~ vcc s2 vcc - 0.2v, > = < = ~ +70c - 8 -
m5m5 y416cwg -55hi, -70hi 2002.04.05 ver. 5.1 4194304 -bit (262144-word by 16-bi t) c mos s tat ic ram mi t subishi lsis ac electrical characteristics (vcc=1.65 ~ 2.3v, unless otherwise noted) input rise time and f all time re f erence le v el output loads 1.65~2.3v v ih =0.7 x vcc+0.2v, v il =0.2v transition is measured 200mv from steady state voltage.(for ten,tdis) 5ns fig.1,cl=30pf cl=5pf (for ten,tdi s) (1) t est conditions suppl y v oltage input pulse 1ttl cl dq fig.1 output load including scope and jig capacitance t cr ns t a (s1) t a (oe) t dis (s1) t dis (oe) t en (s1) t en (oe) t v (a) t a (a) 5 30 ns ns ns ns ns ns ns ns t a (bc1) t a (bc2) t dis (bc1) t dis (bc2) t en (bc1) t en (bc2) ns ns ns ns ns ns 55 20 20 20 20 5 5 5 5 t a (s2) ns t en (s2) 5 ns t dis (s2) ns 20 55 55 hi 4 t su (a-wh) t cw t w (w) t su (a) t su (s1) t su (d) t h (d) t rec (w) t dis (w) t dis (oe) t en (w) t en (oe) ns ns ns ns ns ns ns ns ns ns ns ns ns ns t su (bc1) t su (bc2) t su (s2) ns 20 20 55 45 0 50 5 5 50 50 50 25 0 0 50 s ymbol parameter read c y cle time limits address access time chip select 1 access time chip select 2 access time b y te control 1 access time b y te control 2 access time output enable access time output disable time a ft er s2 low output disable time a ft er s1# high output disable time a ft er bc1# high max min units (2) read cycle output disable time a ft er bc2# high output disable time a ft er oe# high output enable time a f ter s1# low output enable time a f ter s2 high output enable time a f ter bc#1 low output enable time a f ter bc2# low output enable time a f ter oe# low data v alid time a fter address (3) w rite cycle max min limits units write c y cle time write pulse width address setup time address setup time with respect to w# b y te control 1 setup time b y te control 2 setup time chip select 1 setup time chip select 2 setup time data setup time data hold time write reco v er y time output disable time f rom w# low output disable time f rom oe# high output enable time f rom w# high output enable time f rom oe# low s ymbol parameter v oh =v ol =0.9v 55 hi 55 55 55 55 70 hi max min max min 70 hi 10 35 70 25 25 25 25 5 5 5 10 10 25 70 25 25 70 55 0 65 5 5 65 65 65 30 0 0 65 70 70 70 70
m5m5 y416cwg -55hi, -70hi 2002.04.05 ver. 5.1 4194304 -bit (262144-word by 16-bi t) c mos s tat ic ram mi t subishi lsis (note5) (note5) t su (s2) t en (w) 5 t a (a) t a (bc1) t v (a) t dis (bc1) or t dis (bc1) t a (oe) t en (oe) t dis (oe) t cr t h (d) t su (d) dq 1~16 t su (bc1) or t su (bc2) t en (oe) t dis (oe) t w (w) t rec (w) t su (a) t dis (w) t cw t en (s1) w# = "h" le v el a 0~17 dq 1~16 a 0~17 oe# (4)timin g diagrams read cycle (note5) (note5) (note5) (note5) valid data write cycle ( w# control mode ) data in stable (note5) (note5) t a (s1) t dis (s1) s1# (note5) (note5) bc1# , bc2 # t a (bc2) or t en (bc2) t en (bc1) t su (a-wh) (note5) (note5) t su (s1) t a (s2) t dis (s2) s2 (note5) (note5) t en (s2) w# oe# s1# bc1# , bc2 # s2
m5m5 y416cwg -55hi, -70hi 2002.04.05 ver. 5.1 4194304 -bit (262144-word by 16-bi t) c mos s tat ic ram mi t subishi lsis 6 note 5: hatching indicates the state is "don't care". note 6: a write occurs during s1# low, s2 high o v erlaps bc1# and/or bc2# low and w# low. note 8: don't appl y in v erted phase signal externall y when dq pin is in output mode. note 7: when the f alling edge o f w# is simultaneousl y or prior to the f alling edge o f bc1# and/or bc2# or the f alling t h (d) t su (d) dq 1~16 t su (bc1) or t su (bc2) t rec (w) t su (a) t cw a 0~17 w# write cycle (bc# control mode) data in stable (note5) (note5) (note6) (note7) (note5) (note5) s1# edge o f s1# or rising edge o f s2, the outputs are maintained in the high impedance state. bc1# , bc2# (note5) (note5) s2
m5m5 y416cwg -55hi, -70hi 2002.04.05 ver. 5.1 4194304 -bit (262144-word by 16-bi t) c mos s tat ic ram mi t subishi lsis t h (d) t su (d) dq 1~16 t su (s1) t rec (w) t su (a) t cw a 0~17 w# s1# write cycle (s1# control mode) data in stable (note5) (note5) (note6) (note7) (note5) (note5) bc1# , bc2# (note5) (note5) s2 t h (d) t su (d) dq 1~16 t su (s2) t rec (w) t su (a) t cw a 0~17 w# s1# write cycle (s2 control mode) data in stable (note5) (note5) (note6) (note7) (note5) (note5) bc1#,bc2 # (note5) (note5) s2 7
m5m5 y416cwg -55hi, -70hi 2002.04.05 ver. 5.1 4194304 -bit (262144-word by 16-bi t) c mos s tat ic ram mi t subishi lsis 8 t su (pd) t rec (pd) ns ms 0.7 x vcc t su (pd) 1.65v1.65v t rec (pd) bc1# , bc2# vcc-0.2v vcc v 1 .3 vcc (pd) v i (s1) icc (pd) 0.7xvcc bc1# power do wn characteristics (1) electrical characteristics s ymbol parameter test conditions limits min t yp max units power down supply volta ge chip select input s1# power down suppl y c urrent (2) timin g requirements s ymbol parameter test conditions limits min t yp max units power down set up time power down reco v er y t ime (3) timin g diagram bc# control mode on the bc# control mode, the level of s1# and s2 must be fixed at s1#, s2 vcc-0.2v or s2 0.2v v i (bc) byte control input bc1# & bc2# v > = bc2# t su (pd) 1.65v1.65v t rec (pd) vcc s1# s1# control mode on the s1# mode, the level of s2 must be fixed at s2 vcc-0.2v or s2 0.2v. s1# vcc-0.2v > = 0 5 v i (s2) chip select input s2 0.2 0.2v t su (pd) 1.65v1.65v t rec (pd) vcc s2 s2 control mode s2 0.2v a ~ +40c 0.1 - - ~ +85c ~ +25c - 0.2 0.7 1.5 - 10 (1) s1# vcc - 0.2v, > = other inputs = 0 ~ vcc s2 0.2v, (2) other inputs = 0 ~ vcc bc1# and bc2# vcc - 0.2v s1# 0.2v, s2 vcc - 0.2v < = > = (3) > = other inputs = 0 ~ vcc vcc=1.65v 0.7 x vcc 0.7 x vcc 0.7 x vcc 1.65v vcc(pd) 1.3v vcc(pd) 1.65v vcc(pd) 0.7xvcc 1.65v vcc(pd) 1.3v vcc(pd) 1.65v vcc(pd) v 0.2v note 9: typical parameter of icc(pd) indicates the value for the center of distribution at 1.65v, and not 100% tested. < = ~ +70c - 5 - v > = > =
m5m5 y416cwg -55hi, -70hi 2002.04.05 ver. 5.1 4194304 -bit (262144-word by 16-bi t) c mos s tat ic ram mi t subishi lsis 9 keep safety first in your circuit designs! mitsubishi electric corporation puts the maximum effort into making semiconductor products betterand more reliable, but there isalways the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injur y, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non- flammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials these materials are intended as a reference to assist our customers in the selection of the mitsubishi semiconductor product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to mitsubishi electric corporation or a third party. mitsubishi electric cor poration assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by mitsubishi electric corporation without notice due to product improvements or other reasons. it is therefore recommended that customers contact mitsubishi electric corporation or an authorized mitsubishi semiconductor p r oduct distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. mitsubishi electric corporation assumes no responsibility for any damage , liabilit y, o r other loss rising from these inaccuracies or e rrors. please also pay attention to information published by mitsubishi electric corporation by various means, including the mitsubishi semiconductor home page (http://www.mitsubishichips.com). when using any or all of the information contained in these materials, including product data, diagrams, charts, p r o gr ams, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. mitsubishi electric corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. mitsubishi electric corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact mitsubishi electric corporation or an authori zed mitsubishi semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. the prior written approval of mitsubishi electric corporation is necessary to reprint or reproduce in whole or in part these materials. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a license from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distribut o r for further details on these materials or the products contained therein.
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